AMD Epyc Milan, Zen 3 based

Can be fake, but...

AMD Ryzen 9 5900X

• 12 cores only
• IPC improvement of up to 20% (around 3% in real life)
• Boost clocks (for short periods) of up to 5 GHz (+300 MHz improvement over the Ryzen 9 3900XT)
• CPU won't be able to offer much higher sustainable all core clock
• 150W TDP (not real consumption, just spec)
• Real consumption will pass 200w for heavy loads during boosts time or overclock
• Price will jump around 15-20% compared to 3900XT

AMD can repeat stunt they made with client IO die (part of processor that deal with IO and RAM)

X570 chipset had been actually just mostly rewired IO die from Zen 2 CPU.

X670 chipset can be again just die put on separate board.

New rumors

• CPUs will have 5xxx names
• It won't be 16 core CPUs (12 cores tops), at least in retail and at initial stages
• AMD can't make too much fully non defective 8 core chiplets now
• Main issue can be horrible situation with 7nm EUV process on TSMC
• AMD had been forced to use this process as 5nm capacity is literally not available

Note that for Zen 2 and Zen 1 number of total fully nondefective chiplets reached 98% after few months, so almost all of lower end CPUs have intentionally disabled cores and even most of the nonconnected chiplets in Threadrippers had been fully functional.

Unlike the previous generation design where each CCD comprised of two CCX's (Core Complexes), the Zen 3 CCD will consist of a single CCX which will feature 8 cores that can run in either a single-thread mode (1T) or a two-thread mode (2T) for up to 16 threads per CCX. Since the chip houses a maximum of two CCDs, the core and thread count will max out at 16 cores and 32 threads which is the same as the existing flagship AM4 desktop CPU, the Ryzen 9 3950X.

Each Zen 3 core will feature 512 KB of L2 cache for a total of 4 MB of L2 cache per CCD. That should equal 8 MB of L2 cache on a dual CCD CPU. Along with the L2 cache, each CCD will also comprise of up to 32 MB of shared L3 cache. For Zen 2, the L3 cache was split between the two CCX's with each CCX having their own separate (Up To) 16 MB cache. The size of the cache remains the same per CCD but now all cores can share a larger number of L3 cache.

https://wccftech.com/amd-zen-3-ryzen-4000-vermeer-cpus-detailed-up-to-16-cores-32-threads/

New info tells about 10 core model in lineup

Two chiplet versions will be

• 10 cores, with 6 cores intentionally disabled
• 12 cores, with 4 cores intentionally disabled
• 14 cores, AMD thinking on such version also
• 16 cores, all cores are not disabled by special laser

According to rumors for present TSMC 7nm process and small chiplet size usually 85-90% of chiplets have all 8 cores working and 98% have at least 6 out of 8 working. So, almost all 10 core CPUs and most of 12 core ones are being made by disabling perfectly working cores, just out of marketing purposes.

IPC performance increase will be up to + 15% for integer workloads. For EPYC processors with up to 32 cores, AMD wants to achieve a performance increase of + 20% compared to the Rome processors with Zen 2 cores - the single-treaded performance should also increase by + 20%. For the larger EPYC processors with up to 64 cores, AMD expects a performance increase of around 10 to 15%. Apparently, AMD can achieve a higher clock rate for processors with fewer cores, so that the performance increase has a correspondingly higher effect with fewer cores.

Threadripper and Epyc socket will change from Zen 4

With Genoa, AMD is switching from the SP3 to the SP5 platform. The nominal thermal design power ranges from 120 to 240 W, although there are already special models that allow themselves more than 225 W (official TDP limit for normal models). The TDP increases slightly towards the top. AMD gives up platform compatibility with Genoa after three generations. However, due to the use of DDR5 and PCI-Express 5.0 as well as other functions, AMD has no other choice at this point.

AMD might in fact skip desktop 4000 series in favor of 5000.

This can make a lot of sense, as the current 4000 series lineup is extremely misleading.

AMD already introduced the series with Renoir-based Ryzen 4000U and Ryzen 4000H models.

Digitimes, VideoCardz, and RetiredEngineer (twitter) started an intriguing rumor that Ryzen 4000 might end up at 5nm+. Asking around at a reliable place, we have to disappoint some of you as this won't be the case. The Ryzen 4000 series based on Zen 3 core is still at 7nm.

As expected 5nm thing had been idiotic TSMC PR move. As it seems that they don't have 5nm suitable for high powered chips at all now. And wanted to make info clouds for US to make it look that existing 5nm will be suitable for their needs.