Unlike the previous generation design where each CCD comprised of two CCX's (Core Complexes), the Zen 3 CCD will consist of a single CCX which will feature 8 cores that can run in either a single-thread mode (1T) or a two-thread mode (2T) for up to 16 threads per CCX. Since the chip houses a maximum of two CCDs, the core and thread count will max out at 16 cores and 32 threads which is the same as the existing flagship AM4 desktop CPU, the Ryzen 9 3950X.
Each Zen 3 core will feature 512 KB of L2 cache for a total of 4 MB of L2 cache per CCD. That should equal 8 MB of L2 cache on a dual CCD CPU. Along with the L2 cache, each CCD will also comprise of up to 32 MB of shared L3 cache. For Zen 2, the L3 cache was split between the two CCX's with each CCX having their own separate (Up To) 16 MB cache. The size of the cache remains the same per CCD but now all cores can share a larger number of L3 cache.
https://wccftech.com/amd-zen-3-ryzen-4000-vermeer-cpus-detailed-up-to-16-cores-32-threads/
Now all Cores can share larger amounts of cache and add to that latency !!! Plop
New rumors
Note that for Zen 2 and Zen 1 number of total fully nondefective chiplets reached 98% after few months, so almost all of lower end CPUs have intentionally disabled cores and even most of the nonconnected chiplets in Threadrippers had been fully functional.
Specific models
AMD can repeat stunt they made with client IO die (part of processor that deal with IO and RAM)
X570 chipset had been actually just mostly rewired IO die from Zen 2 CPU.
X670 chipset can be again just die put on separate board.
Small leak on that happened with Zen 3 original plans to have 4 threads per core
Original Zen 3 design had 4 hyperthreading threads per each core.
But AMD could not make it work good due to thermal issues
As you have more threads you have more parts of each core used and thermal situation becomes worse. In benchmark case CPU can be forced to drop frequency up to 2 times to keep things under control.
In real life of modern 7nm processors they have parts of CPU constantly turned off to limit thermal happening due to leakage. And you can't do it adding too much threads.
Intel also needed to slow down CPU during heavy AVX-512 loads.
AMD Ryzen 9 5900X
Can be fake, but...
Livestream
Some slides
UK prices
EU prices
Note that AMD also excluded coolers from all but cheapest 6 core models, so profits (including saving on cooler and price rise) are around $100 bigger for most models now.
AMD IO die part
It is exactly same as in Zen 2, cheap as shit, 12nm thing.
x570 chipset is also exactly same die :-)
AMD had much better memory controller in mobile and hybrid latest CPUs, but did not updated IO chiplet, as this required changing masks (aka few less Ferrari cars for AMD top management). All extra profits will be guided to more buybacks and top managers bonuses, none into development.
On BIOS updates
Taiwan manufacturers current plans
ASUS will provide updated BIOS' for the X470 and B450 chipsets based on AMD's current release schedule of new AGESA code in January 2021. This original report was based on incorrect information.
MSI on motherboards support
Main reason that AMD provides fully solid and encrypted AGESA or AMD Generic Encapsulated System Architecture BIOS part. Such way they can prevent old chipset from getting modern CPU support.
Exactly same way they disabled PCIe 4.0 support on older chipsets (actually main M.2 and PCIe x16) spots onall B450 and B350 motherbaords can work in PCIe 4.0.
Such way corporation is making tens of billions of damages and huge ecology impact by forcing unnecessary updates, and all for 3-4 main investors and less than 100 of top managers to get their big cut. This guys are open criminals.
Some new benchmarks
BIOSTAR also will do standard things and add support to some older MBs, but not 3xx series.
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