The PCI-SIG consortium, which deals with the development and standardization of PCI, announced that the final specifications of the new bus version will be adopted in 2025.

A single PCIe 7.0 lane can provide data transfer rates of up to 128 GT/s (gigatransactions per second) or 32 GB/s. Thus, 16 PCIe lanes in duplex (both directions) will be able to transfer data at speeds up to 512 GB / s, which is twice the capabilities of the PCIe 6.0 standard. And an SSD with a PCIe 7.0 x4 interface can theoretically provide read and write speeds close to 64 GB / s in each direction - the limit of upcoming drives with PCIe 5.0 x4 is 15.7 GB / s.

The new PCIe 7.0 standard will require the use of more complex and expensive board layouts. However, the PCI-SIG consortium notes that the choice of the number of PCIe 7.0 lanes will remain with the manufacturers, since not in all cases there is a need to use all 16 lanes. In addition, the whole new bus standard can be easily scaled up. It will be able to find application in a great variety of different electronic devices, ranging from mobile devices to supercomputers.