IBM’s new 2nm chip features about 333 million transistors per square millimeter (MTr/mm2). For comparison, TSMC’s most advanced chips, built using its 5nm process, feature about 173 million transistors per square millimeter (MTr/mm2), while Samsung’s 5nm chips feature about 127 MTr/mm2.

Note that it is fake info, as companies mention that they mean some abstract transistors, not real ones you can use in CPU logic, for example, where you need proper heat management, interference, more metal layers and so on.

5nm is also utter marketing, real progress stopped at around 20-22nm, after this 14nm could shrink only certain features, "7nm" by TSMC being 12-14nm in reality even for such features, and 5nm being 7nm on steroids where focus was on SRAM, leaks and similar parts.

Now back to 2nm fakes, if we use numbers provided 173 millions must have turned into 1084 billions (2.5x2.5 = 6.25 times), but in reality it is not even 2 times.

Size of key features is reduced 40% tops (173×(1,4×1,4) = 339,08), but transistors can't be made smaller, so now all this went in rising vertical part (whole progress since 22nm had been vertical already, even most 22nm chips used this a lot).