JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD300-5: SPD5118, SPD5108 Hub & Serial Presence Detect Device Standard. Serial Presence Detect, or SPD, has been incorporated into every JEDEC standard memory module for over 20 years as a configuration memory storing operation parameters and capabilities for the module, read by the host system over a 1MHz I2C serial bus. This new SPD device specification represents a major evolution of the traditional SPD by providing a load isolation hub function that allows multiple serial bus devices on any module while increasing serial bus speed to 12.5MHz over a new 1.0V JEDEC Module SidebandBus, which is a superset of the MIPI I3C Basic bus developed by the MIPI Alliance.

Other technical specifications of the new SPD devices include a doubling of storage capacity to 1024 bytes segmented into 16 individually write protectable regions, up to eight individually addressable SPDs on a bus using a single resistor to ground to select a device address, and a flexible I/O voltage range from 1.0V to 3.3V.

https://www.jedec.org/news/pressreleases/jedec-announces-publication-new-serial-presence-detect-device

Size increase actually did not require any big moves, just small evolution changes.

Let's look at MIPI licensing

MIPI’s regular IPR terms apply to the full MIPI I3C specification. MIPI’s terms require that members make licenses available only to other members, as described in the MIPI Membership Agreement and MIPI Bylaws. To benefit from the license commitments, a party must be a MIPI member.

So, all the fuss here is fuzzy licensing and new "standard" of simple and long known thingy (hence i2c is declared bad).

As for illusive speed advantages, no one prevents to cache SPD data in motherboard own non volatile memory (and all modern ones has plenty of it).