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Why SATA development stopped?
  • Vitaliy_KiselevVitaliy_Kiselev

    Let's look at SATA 3.0 - native transfer rate is 6.0 Gbit/s; 8b/10b encoding, maximum uncoded transfer rate is 4.8 Gbit/s (600 MB/s).

    This is using two differential pairs:

    image

    image

    Let's check PCIe that Thunderbolt is using.

    PCIe 2.0 standard doubles the transfer rate compared with PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s.

    PCI Express 3.0 carry a bit rate of 8 gigatransfers per second (GT/s), PCI Express 3.0 upgrades the encoding scheme to 128b/130b from the previous 8b/10b encoding, reducing the bandwidth overhead from 20% of PCI Express 2.0 to approximately 1.54%. PCI Express 3.0's 8 GT/s bit rate effectively delivers 985 MB/s per lane, nearly doubling the lane bandwidth relative to PCI Express 2.0

    A x1 connection, the smallest PCIe connection, has one lane made up of four wires.

    So, even years ago we had perfectly ready method to get 985 MB/s per lane, could even add internal switch for controller to go into PCIe mode using same wires.

    image

    So, decision to stop SATA development had been intentional and not based on any real limits for now, just wanted to drop compatibility layers and simplify interface.

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  • 1 Reply sorted by
  • Vitaliy_KiselevVitaliy_Kiselev

    Interesting fun fact, SATA 3.5 specs released

    The maximum exchange rate remained unchanged and froze at 6 Gbit / s. But the developers of the standard promise to increase overall performance and improve integration with other I / O standards.

    The first is the technical function of Device Transmit Emphasis for Gen 3 PHY. It allows you to focus on the transmitter, which equates SATA with other I / O solutions when measuring their characteristics. This function should help at the stage of testing and integration of interfaces of new devices.

    Secondly, the SATA specifications have a function for determining the ordering of NCQ commands or Defined Ordered NCQ Commands. It allows the host to specify the relationship between the teams in the queue and sets the order in which these commands are processed.

    The third new extension in SATA Revision 3.5 is the Command Duration Limit Features. It is designed to reduce delays by allowing the host to define the quality of service categories through more detailed control of the properties of commands.

    Looks for me as big warning, such way SATA guys ask for new transfer to keep standard without development.

    Without any issues this guys can make speed 4x-8x from current, almots nothing to do.

    But it will also mean that value of M2 ports will drop and it'll be much harder to get excess profits for boards with more such ports.

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