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More layers and more TLC in NAND memory
  • SK Hynix plans to launch the mass-production of 48-stack 3D NAND flash memory chips from the end of this month. This is the second time among global memory chip makers to do so behind Samsung Electronics.

    In a situation where the flat micro-processing technology reached its limit at around 10 nanometers, 3D NAND was developed as an alternative to overcome the limit.

    SK Hynix will increase its monthly 3D NAND output from 10,000 units in the third quarter of last year to 20,000-30,000 units by the end of this year, with the share of 3D NAND in its overall NAND output rising to around 15 percent.

    The share of 3D NAND in NAND companies' overall production is forecast to rise to 57.8 percent in 2017 from 23.6 percent in 2016 and 6.7 percent in 2015.

    SK Hynix is now developing the next-generation 72-stack 3D NAND and is expected to begin the mass-production from the latter half of next year.

    Note that it is almost all TLC memory, not only it can have speed issues but rewrite cycles are lower and lower.

    Today's commodity 2D MLC flash has raw wear-out in the 2,000 to 3,000 write cycle range.

    Samsung TLC specs at 1000 cycles.

    2D QLC (4 bit one) memory must drop to 500 cycles.

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    Samsung is very optimistic, but not all agree with this.

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