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PCIe 5.0 finalized now, with 4x speed, Apple can be first to use it
  • Such situation happened due to extreme delay with PCIe 4.0, and it will be only upcoming AMD 3000 series CPUs that will befirst to implement such standard (even on older motherboards some slots will start to work in it, same as it happened with HDMI after 2200G/2400G introduction).

    Rumors in industry are that Apple aims to use PCIe 5.0 in all upcoming 8/16 cores ARM CPUs made for their upcoming iOS based notebooks lines. Of course Thunderbolt via USB-C ports will also greatly benefit from this change with corresponding speed increases.





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  • 11 Replies sorted by
  • New TB, new TB, new TB. :). 10 lane TB plug please, for extra wide data rate.

  • The big tradeoff of the higher speeds is that signals won’t travel as far on existing designs. In the days of PCIe 1.0, the spec sent signals as much as 20 inches over traces in mainstream FR4 boards, even passing through two connectors. The fast 4.0 signals will peter out before they travel a foot without going over any connectors.

    System makers are sharpening their pencils on the costs of upgrading boards and connectors, adding chips to amplify signals, or redesigning their products to be more compact.

    Retimer chips for a full 16-lane full PCIe 4.0 could cost $15 to $25 — if you can find them. Upgrading an adapter card from Megtron-2 to Megtron-4 materials might only add a dollar or so. However, the cost of a similar upgrade for a motherboard is about $100, and if the upgrade is to even higher quality Megtron-6 it would cost about $300.

    PCIe 4.0 signals are only travelling three to five inches, said the CEO of PLDA Inc., a designer of PCIe controller cores that came out with 4.0 products three years ago.

    “We cannot use FR4. We needed to move to Megtron-6; that’s really clear to me. If you want to get more distance, you need to use retimers, and that’s a bit expensive and tricky.”

    “What we have been using for 4.0 and expect to use for 5.0 is twinax cables and firefly connectors, The cost is very low compared to retimers, you can get whatever you want in distance, and the latency is really good.”

    The industry has thrived for nearly 18 years on the PCIe mechanicals, but that it’s time for a change.

    The GenZ interconnect group is already exploring new designs that put a connector 60 mm closer to a processor.

    The 4.0 standard supports FR4 boards for all uses but the longest reaches where retimers are needed, said Yanes. Whether boards will have to move off of FR4 to get the 5.0 speeds “is still part of the discussion … some motherboards may only have a couple of 5.0 slots or attach points.”

    So, expect all consumer platforms to have one fast PCIe slot, and may be one extra M.2, al else will be slow same PCIe 3.0.

  • I'm not sure why anyone would want PCIe 4.0 or 5.0, as modern graphics cards are not even saturating PCIe 3.0 16x. Where would anybody need more data throughput (maybe except for servers)?

  • @Psyco

    It is simple.

    • SSD drives are now limited by PCIe 3.0 x4
    • Chipset link is PCIe x4 only now, so copy from one fast SSD to another is limited a lot
    • InfiniBand and high speed Ethernet cards, now require x8-x16 slots

    This year we will see AMD adding PCIe 4.0 mostly due to first two points.

  • @Vitaliy_Kiselev

    Who needs that much data moved that quickly?

    "Office"-User - no.

    The usual "high end" gamer - not really.

    Videoblogger - also no (I shoot BMD cameras in RAW and it piles up to 1TB quite fast, but even that amount of data is copied bevor I finish my coffee).

    More professional production - yes, but they can afford a HEDT like Threadripper or Xeons with plenty of PCIe lanes. Just put NVMe raid cards in 16x slots or the fast network cards.

    Don't get me wrong: Progress is good and faster PCIe lanes are a step in the right direction. But the drawbacks (extremly short wires) of PCIe 4.0/5.0 are really bad... and expensive. So, why would anybody throw money at it?

    It really does only make sense to have PCIe 4.0/5.0 between the CPU and chipset (as they are really close together anyway) and then have MUCH MORE PCIe 3.0 16x slots on the mainboard.

  • @Psyco

    No one asks office user as it is up to department to decide.

    Videoblogger - also no (I shoot BMD cameras in RAW and it piles up to 1TB quite fast, but even that amount of data is copied bevor I finish my coffee).

    People are different, and not all take during coffee during copy.

    On any consumer platform if you use two GPUs you can't use Infiniband anymore.
    For example, to edit heavy footage directly on server SSD storage.

    More professional production - yes, but they can afford a HEDT like Threadripper or Xeons with plenty of PCIe lanes. Just put NVMe raid cards in 16x slots or the fast network cards.

    It is consumer products that need PCIe 4.0 and 5.0 the most, exactly as it is total shortage of lines. And yes, you can't do more PCIe lines keeping same price.
    They can remove RGB leds, of course, but no sane market manager will do it, as RGB leds sell better :-)

    It really does only make sense to have PCIe 4.0/5.0 between the CPU and chipset (as they are really close together anyway) and then have MUCH MORE PCIe 3.0 16x slots on the mainboard.

    Comment makes no sense. Open any of my recent topics in Storage and Computer and look at real chipset limits and such.

  • Intel plans to have it working in 2021 for server segment, most probably we will see it in consumer segment around 2022-24


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  • PCI-SIG® today announced the release of PCI Express® (PCIe®) 5.0 specification, reaching 32GT/s transfer rates, while maintaining low power and backwards compatibility with previous technology generations.

    “New data-intensive applications are driving demand for unprecedented levels of performance,” said Al Yanes, PCI-SIG Chairman and President. “Completing the PCIe 5.0 specification in 18 months is a major achievement, and it is due to the commitment of our members who worked diligently to evolve PCIe technology to meet the performance needs of the industry. The PCIe architecture will continue to stand as the defacto standard for high performance I/O for the foreseeable future.”

    “For 27 years, the PCI-SIG has continually delivered new versions of I/O standards that enable designers to accommodate the never-ending increases in bandwidth required for next generation systems, while preserving investments in prior generation interfaces and software,” noted Nathan Brookwood, research fellow at Insight 64. “Over that period, peak bandwidth has increased from 133 MB/second (for the first 32-bit parallel version) to 32 GB/second (for the V4.0 by16 serial version), a 240X improvement. Wow! The new PCIe 5.0 standard doubles that again to 64 GB/second. Wow2. We have come to take this increased performance for granted, but in reality, it takes a coordinated effort across many members of the PCI-SIG to execute these transitions so seamlessly.”

    PCIe 5.0 Specification Highlights

    • Delivers 32 GT/s raw bit rate and up to 128 GB/s via x16 configuration
    • Leverages and adds to the PCIe 4.0 specification and its support for higher speeds via extended tags and credits
    • Implements electrical changes to improve signal integrity and mechanical performance of connectors
    • Includes new backwards compatible CEM connector targeted for add-in cards
    • Maintains backwards compatibility with PCIe 4.0, 3.x, 2.x and 1.x

    The new specification increases performance in the high-performance markets including artificial intelligence, machine learning, gaming, visual computing, storage and networking.

    To learn more about the PCIe 5.0 specification, visit PCI-SIG members can download the full specification here.

  • Astera Labs Inc., in collaboration with Synopsys, Inc. (Nasdaq: SNPS), and Intel (Nasdaq: INTC), today announced an industry-first demonstration of a complete PCI Express® (PCIe®) 5.0 system, delivering 32 GT/s speeds for next-generation server workloads. The end-to-end solution showcases system-level multi-vendor interoperability between Intel's PCIe 5.0 test chip, Synopsys' silicon-proven DesignWare® Controller and PHY IP for PCIe 5.0, and Astera Labs' industry-first Smart Retimer SoC for PCIe 5.0. The companies will demonstrate the solution at the PCI-SIG Developers Conference in Taipei, October 28-29.

  • image

    Synopsys, Inc. announced its collaboration with Intel to achieve successful system-level interoperability between the Synopsys DesignWare Controller and PHY IP for PCI Express 5.0 and future Intel Xeon Scalable processors (codename Sapphire Rapids). The full-system interoperability, a key milestone in Synopsys and Intel's ongoing collaboration, enables the ecosystem to confidently use the companies' proven technologies to accelerate development of their PCIe 5.0-based products in high-performance computing and AI applications. The DesignWare IP for PCI Express 5.0 has been licensed over a hundred times by customers across all key market segments, delivering the lowest latency and highest throughput IP compared to other solutions in the industry.

    "Synopsys continues to collaborate with industry leaders like Intel to deliver high-quality IP that help designers address the bandwidth, power, area, and latency demands for the new era of high-performance computing systems," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "Achieving successful interoperability between Synopsys' DesignWare IP for PCIe 5.0 and Intel Xeon Scalable processors validates that the IP functions as intended with Intel's industry-standard PCIe 5.0 products, accelerating the path to first-silicon success with less risk."

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  • From AMD interview

    IC: Can you talk about AMD’s goals with regards to IO and power consumption - we’ve seen AMD deliver PCIe Gen4 in 7nm but the IO die is still based in 12/14nm from Global Foundries. I assume it is a key target for improvements in the future just not this time around?

    MP: It’s generational - if you look to the future we drive improvements in every generation. So you will see AMD transition to PCIe Gen 5 and that whole ecosystem. You should expect to hear from us in our next round of generational improvements across both the next-gen core that is in design as well as that next-gen IO and memory controller complex.