Updates

• Tremont microarchitecture supports many of the same features as those found on the Ice Lake Client microarchitecture."
• Tremont will be the first Intel Atom processors to support Intel Speed Shift technology.
• Support for parallel out-of-order instruction decode
• An increase in the size of reorder buffer, load buffer, store buffer, and reservation stations for deeper out-of-order execution and higher cache bandwidth
• 33-percent increase in the size of L1 data cache (from 24KB to 32KB)
• 100-percent increase in the load bandwidth and store bandwidth
• L2 cache sizes ranging from 1MB to 4.5MB depending on the SoC design
• Support for new instructions for encryption, power management, cache, and more

More info at https://software.intel.com/content/dam/develop/public/us/en/documents/64-ia-32-architectures-optimization-manual.pdf